Circuit depth is the number of time steps (layers) required to execute a quantum circuit when gates that act on disjoint qubits are parallelized within the same layer. It is a critical metric because each layer takes time to execute, and the total circuit execution time (depth multiplied by gate time per layer) must fit within the qubits' coherence window. Deeper circuits accumulate more errors from decoherence and imperfect gates, limiting the computations achievable on near-term hardware.
For example, a 100-qubit circuit with depth 1,000 on a superconducting processor with 200-nanosecond two-qubit gates takes approximately 200 microseconds to execute — comparable to or exceeding typical T2 coherence times. This means the qubits at the beginning of the circuit will have substantially decohered by the time the circuit completes. In contrast, the same circuit on trapped ions with 10-microsecond gates would take 10 milliseconds, well within their seconds-long coherence times but much longer in absolute wall-clock time.
Reducing circuit depth is a major focus of quantum algorithm and compiler design. Techniques include parallelizing independent operations, optimizing gate cancellations, exploiting hardware-specific gate decompositions, and designing algorithms with inherently shallow circuits. The NISQ era is fundamentally defined by circuit depth limitations — algorithms must be designed to fit within the coherent computation window of available hardware, which currently limits practical circuits to roughly 100-1,000 layers depending on the platform.